Infineon Introduces New OptiMOS Source Bottom-Mount Power MOSFETs

High power density, excellent performance and ease of use are key requirements for today’s power system designs. To this end, Infineon has introduced a new generation of OptiMOS Source-Down (SD) power MOSFETs to provide a practical solution to the design challenges in end applications. The power MOSFETs are available in a PQFN package measuring 3.3×3.3mm2 and support a wide voltage range from 25V to 100V. This package sets a new industry benchmark for power MOSFET performance by enabling higher efficiency, higher power density, industry-leading thermal performance metrics, and lower BOM costs. The device has a wide range of applications, covering motor drives, SMPS for servers, telecom and OR-ing, and battery management systems.

Infineon introduces the new OptiMOS source-bottom power MOSFETs

Compared to the traditional Drain-Down package, the latest source-bottom package technology allows the device form factor to be close to that of a bare chip. In addition, this innovative packaging technology also reduces losses and further enhances the overall performance of the device. The use of a source-bottom package can reduce RDS(on) by 30% compared to the most advanced drain-bottom package. Key benefits of this technology innovation for system design include: reduced form factor, from SuperSO8 5x6mm2 package to PQFN 3.3×3.3mm2 package, can reduce the occupied space by about 65%, allowing more efficient use of available space, thus increasing the power density and system efficiency of the end system.

In addition, heat is transferred to the PCB via a thermal pad in the source bottom-mount package, rather than through internal lead bonding or copper entrapment design, thereby improving heat dissipation. This also allows the junction-to-case thermal resistance (RthJC) to be reduced from 1.8K/W to 1.4K/W, a reduction of more than 20%, enabling excellent thermal performance. Infineon is currently offering two models with different board areas, which are SD standard gate layout and SD gate centered layout. In the standard gate layout, the location of the electrical connections remains the same, facilitating a simple and direct replacement of the standard drain bottom package with a new source bottom package, while in the center gate layout package, the gate pins are moved to a central location to allow multiple MOSFETs to be connected in parallel. Both types allow for optimized PCB layout, resulting in reduced parasitic effects, improved PCB loss, and ease of use.


OptiMOS Source Bottom Power MOSFETs are now available in a PQFN 3.3×3.3mm2 package supporting a wide voltage range from 25V to 100V and are available in two models with different board footprints.

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